# Copyright (c) 2008-2012 BEEcube, Inc. All rights reserved. You may copy
# and modify these files for your own internal use solely with BEEcube 
# hardware systems using Xilinx programmable logic devices and the Xilinx
# EDK system. No rights are granted to redistribute these files unless 
# they are distributed in BEEcube hardware systems using Xilinx 
# programmable logic devices. 
# 
# THIS SOURCE MATERIAL IS PROVIDED "AS IS" WITH ALL FAULTS, AND THE ENTIRE 
# RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE 
# AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR 
# ADVICE, WHETHER GIVEN BY BEECUBE, OR ITS AGENTS OR EMPLOYEES. BEECUBE 
# MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, 
# REGARDING THE SOURCE MATERIAL, INCLUDING ANY WARRANTIES OF 
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# NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL BEECUBE BE 
# LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR 
# INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING 
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# LIABILITY.
#!/bin/bash

BRAM_BA=0x10100000
REG_IN_BA=0x10102000
REG_OUT_BA=0x10102100

SRC_IP=192.168.100.101
DST_IP=192.168.100.100
DST_PORT=48867

BRAM_SIZE=$[2**11]
DRAM_SIZE=$[512*$[1024*1024]]

#echo "Host IP Address:"
#read SRC_IP 
#echo "BEE3 IP Address"
#read DST_IP 
#echo "BEE3 Port"
#read DST_PORT
#echo "Test Register BaseAddress"
#read REG_BA
#echo "Test BRAM BaseAddress"
#read BRAM_BA

echo "Include DRAM test? [y/n]"
read TEST_DRAM

echo "Test REG RW..."
STAT=1
../examples/xge_regwrite $SRC_IP $DST_IP $DST_PORT $REG_IN_BA 0x12345678 >log
RD_LOG=`../examples/xge_regread $SRC_IP $DST_IP $DST_PORT $REG_OUT_BA`
echo $RD_LOG >>log 
if [ `echo $RD_LOG | grep -c 0x12345678` = 0 ]; then
	STAT=0
fi

../examples/xge_regwrite $SRC_IP $DST_IP $DST_PORT $REG_IN_BA 0xFEDCBA98 >>log
RD_LOG=`../examples/xge_regread $SRC_IP $DST_IP $DST_PORT $REG_OUT_BA`
echo $RD_LOG >>log 
if [ `echo $RD_LOG | grep -c 0xfedcba98` = 0 ]; then
	STAT=0
fi

if [ $STAT = 1 ]; then
	echo REG R/W Passed
else
	echo REG R/W Failed. Check log for more details.
fi

STAT=1
echo Test BRAM R/W...
TSIZE=$[$BRAM_SIZE/8];
while [ $TSIZE -le $BRAM_SIZE ];
do
	# Create test file
	../test/testfile_gen $[$TSIZE/4]
	../examples/xge_bramwrite $SRC_IP $DST_IP $DST_PORT $BRAM_BA testFile >>log
	../examples/xge_bramread $SRC_IP $DST_IP $DST_PORT $BRAM_BA $TSIZE dump >>log
	diff dump testFile
	if [ $? != 0 ]; then
		STAT=0
		echo Test BRAM R/W with size $TSIZE ... Failed 
	else
		echo Test BRAM R/W with size $TSIZE ... Succeeded
	fi
	TSIZE=$[$TSIZE+$[$BRAM_SIZE/4]]
done 
if [ $STAT = 1 ]; then
	echo Test BRAM R/W Passed
else
	echo Test BRAM R/W Failed
fi
if [ $TEST_DRAM = y ]; then
    STAT=1
    echo Test DRAM R/W...
    TSIZE=$[256*1024];
    while [ $TSIZE -le $DRAM_SIZE ];
    do
    	# Create test file
    	../test/testfile_gen $[$TSIZE/4]
    	../examples/xge_dramwrite $SRC_IP $DST_IP $DST_PORT 0 testFile >>log
    	../examples/xge_dramread $SRC_IP $DST_IP $DST_PORT 0 $TSIZE dump >>log
    	diff dump testFile
    	if [ $? != 0 ]; then
    		STAT=0
    		echo Test DRAM R/W with size $TSIZE ... Failed
    	else
    		echo Test DRAM R/W with size $TSIZE ... Succeeded
    	fi
    	TSIZE=$[$TSIZE*2]
    done 
    if [ $STAT = 1 ]; then
    	echo Test DRAM R/W Passed
    else
    	echo Test DRAM R/W Failed
    fi
fi
    
